hv5122 features processed with hvcmos ? technology output voltages to 225v using a ramped supply voltage sink current minimum 100ma shift register speed 8.0mhz strobe and enable inputs cmos compatible inputs forward and reverse shifting options hi-rel processing av ailable ? ? ? ? ? ? ? ? general description the hv5122 is a low voltage serial to high voltage parallel converter with open drain outputs. this device has been designed for use as a driver for ac electroluminescent displays. they can also be used in any application requiring multiple output high voltage current sinking capabilities such as driving inkjet and electrostatic print heads, plasma panels, vacuum ?uorescent, or large matrix lcd displays. this device consists of a 32-bit shift register and control logic to perform the output enable and all-on functions. data is shifted through the shift register on the high to low transition of the clock. the hv5122 shifts in the counter-clockwise direction when viewed from the top of the package. a data output buffer is provided for cascading devices. this output re?ects the current status of the last bit of the shift register. operation of the shift register is not affected by the oe(output enable) or the str (strobe) inputs. the hv5122 has been designed to be used in systems which either switch off the high voltage supply before changing the state of the high voltage outputs or which limit the current through each output. functional block diagram 32-channel serial to parallel converter with open drain outputs hv out 2 ? ? ? 28 additional outputs ? ? ? output enable data input clock data ou t hv out 32 strobe hv out 1 hv out 31 32 bi t static shif t register
2 hv5122 44-lead quad cerpac package outline (dj) .650x.650in body, .190in height (max), .050in pitch ordering information device package options 44-lead quad cerpac chip carrier .650x.650in body .190in height (max) .050in pitch 44-lead quad plastic gullwing 10.00x10.00mm body 2.45mm height (max) 0.80mm pitch 44-lead quad plastic chip carrier .653x.653in body .180in height (max) .050in pitch hv5122 hv5122dj* hv5122pg-g hv5122pj-g -g indicates package is rohs compliant (green) * hi-rel processing available absolute maximum ratings supply voltage, v dd -0.5v to +15v supply voltage, v pp -0.5v to +250v logic input levels -0.5v to v dd +0.5v ground current 1 1.5a continuous total power dissipation 2 plastic ceramic 1200w 1500w operating temperature range plastic ceramic -40 o c to +85 o c -55 o c to +125 o c storage temperature range -65 o c to +150 o c lead temperature 3 260 o c parameter value pin con?gurations notes: duty cycle is limited by the total power dissipated in the package. for operation above 25c ambient derate linearly to maximum operatingtemperature at 20mw/c for plastic and at 15mw/c for ceramic. 1.6mm (1/16 inch) from case for 10 seconds 1. 2. 3. 1 44 6 40 1 44 product marking absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packagin g *may be part of top markin g top marking bottom marking y y w w hv5122pg l l l l l l l l l cccccccc aa a yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* = green packagin g *may be part of top marking top marking bottom marking yyww hv5122pj llllllllll ccccccccccc aaa 44-lead quad plastic gullwing (pg) 44-lead quad plastic chip carrier (pj) 44-lead quad plastic gullwing (pg) 44-lead quad plastic chip carrier (pj) 1 44 6 40 44-lead quad cerpac chip carrier (dj) yy = year sealed ww = week sealed l = lot number c = country of origin* a = assembler id* *may be part of top marking top marking bottom marking yyww hv5122dj llllllllll ccccccccccc aaa 44-lead quad plastic chip carrier (dj)
3 hv5122 sym parameter min max units conditions electrical characteristics (over recommended operating conditions unless otherwise speci?ed) dc characteristics i dd v dd supply current - 15 ma f clk = 8.0mhz, f data = 4.0mhz i ddq quiescent v dd supply current - 100 a all v in = 0v i o(off) off-state output current - 10 a all outputs high, all sws parallel i ih high level logic input current - 1.0 a v ih = 12v i il low level logic input current - -1.0 a v il = 0 v oh high level output data out v dd -1.0v - v i dout = -100a v ol low level output voltage hv out - 15 v i hvout = +100ma data out - 1.0 i dout = +100a v oc hv out clamp voltage - -1.5 v i ol = -100ma power-up sequence power-up sequence should be the following: connect ground apply v dd set all inputs to a known state power-down sequence should be the reverse of the above. 1. 2. 3. sym parameter min typ max units recommended operating conditions v dd logic voltage supply 10.8 12 13.2 v hv out high voltage output -0.3 - 225 v v ih high-level input voltage v dd -2.0 - v dd v v il low-level input voltage 0 - 2.0 v f clk clock frequency - - 8.0 mhz t a operating free-air temperature plastic -40 - +85 o c ceramic -55 - +125 ac characteristics (v dd = 12v, t a = 25c) sym parameter min max units conditions f clk clock frequency - 8.0 mhz --- t w clock width, high or low 62 - ns --- t su data setup time before clk falls 25 - ns --- t h data hold time after clk falls 10 - ns --- t on turn-on time, hv out from strobe - 500 ns r l = 2.0k? to 200v t dhl data output delay after h to l clk - 100 ns c l = 15pf t dlh data output delay after l to h clk - 100 ns c l = 15pf
4 hv5122 switching waveforms data in data valid 1 clock data out data out strobe t dl h t su t h t wl t wh t dh l hv out 50% 5 0% 50 % 50 % 50% 15 v t on 12 v 0v 12 v 0v function table function inputs outputs data clk oe strobe shift reg 1 2...32 hv outputs 1 2...32 data out all on x x x l ... on on...on all off x x l h ... off off...off load s/r h or l l h h or l ... off off...off - output enable x h or l h h h or l ... on or off ... notes: h = high level, l = low level, x = irrelevant, = high-to-low transition = dependent on previous stages state before the last clk: high-to-low transition input and output equivalent circuits vdd input gnd hv ou t logic inputs gnd data out logic data output high voltage outputs vdd hv in gnd
5 hv5122 hv5122pg pin function description 1 hv out 11 high voltage outputs. 2 hv out 12 3 hv out 13 4 hv out 14 5 hv out 15 6 hv out 16 7 hv out 17 8 hv out 18 9 hv out 19 10 hv out 20 11 hv out 21 12 hv out 22 13 hv out 23 14 hv out 24 15 hv out 25 16 hv out 26 17 hv out 27 18 hv out 28 19 hv out 29 20 hv out 30 21 hv out 31 22 hv out 32 23 data out data output for cascading to the data input of the next device. 24 n/c no connect. 25 26 27 28 oe output enable input. when oe is low, all hv outputs are forced into a low state, regardless of data in each channel. when oe is high, all hv outputs re?ect data latched. 29 clk data shift register clock. input are shifted into the shift register on the positive edge of the clock. 30 gnd logic and high voltage ground. 31 vdd low voltage logic power rail. 44-lead pqfp pin assignment (pg)
6 hv5122 hv5122pg pin function description 32 str strobe. 33 data in serial data input. data needs to be present before each rising edge of the clock. 34 n/c no connect. 35 hv out 1 high voltage outputs. 36 hv out 2 37 hv out 3 38 hv out 4 39 hv out 5 40 hv out 6 41 hv out 7 42 hv out 8 43 hv out 9 44 hv out 10 44-lead plcc pin assignment (dj/pj) hv5122pj pin function function 1 hv out 16 high voltage outputs 2 hv out 17 3 hv out 18 4 hv out 19 5 hv out 20 6 hv out 21 7 hv out 22 8 hv out 23 9 hv out 24 10 hv out 25 11 hv out 26 12 hv out 27 13 hv out 28 14 hv out 29 15 hv out 30 16 hv out 31 17 hv out 32
7 hv5122 hv5122pj pin function function 18 data out data output for cascading to the data input of the next device. 19 n/c no connect. 20 21 22 23 oe output enable input. when oe is low, all hv outputs are forced into a low state, regardless of data in each channel. when oe is high, all hv outputs re?ect data latched. 24 clk data shift register clock. input are shifted into the shift register on the positive edge of the clock. 25 gnd logic and high voltage ground. 26 vdd low voltage logic power rail. 27 str strobe. 28 data in serial data input. data needs to be present before each rising edge of the clock. 29 n/c no connect. 30 hv out 1 high voltage outputs. 31 hv out 2 32 hv out 3 33 hv out 4 34 hv out 5 35 hv out 6 36 hv out 7 37 hv out 8 38 hv out 9 39 hv out 10 40 hv out 11 41 hv out 12 42 hv out 13 43 hv out 14 44 hv out 15
8 hv5122 44-lead quad cerpac package outline (dj) .650x.650in body, .190in height (max), .050in pitch .150 ma x .040 x 45 o 1 .075 ma x 6 40 d d1 e1 e to p v iew v iew b a a2 a1 seating plane e b note 1 (index area) .035 x 45 o 0.25 max 3 places .025 mi n vi ew b 44 b1 horizontal side v iew ve rtical side v iew symbol a a1 a2 b b1 d d1 e e1 e dimension (inches) min .155 .090 .060 ref .017 .026 .685 .630 .685 .630 .050 bsc nom .172 .100 .019 .029 .690 .650 .690 .650 max .190 .120 .021 .032 .695 .665 .695 .665 jedec registration mo-087, variation ab, issue b, august, 1991. drawings not to scale . supertex doc. #: dspd-44cerpacdj, version d090808. note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
9 hv5122 44-lead pqfp package outline (pg) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch symbol a a1 a2 b d d1 e e1 e l l1 l2 dimension (mm) min 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* 0.80 bsc 0.73 1.95 ref 0.25 bsc 0 o nom - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5 o max 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7 o jedec registration mo-112, variation aa-2, issue b, sep.1995. * this dimension is not speci?ed in the original jedec drawing. the value listed is for reference only. drawings not to scale. supertex doc. #: dspd-44pqfppg, version a090808. 1 44 seating plane gauge plane l l1 l2 vi ew b vi ew b seating plane top view d d1 e e1 b e side view a2 a a1 note 1 (index area d1/4 x e1/4) note: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. website: http//www .supertex.com . ?2008 all rights reserved. unauthorized use or reproduction is prohibited . 1235 bordeaux drive, sunnyvale, ca 9408 9 te l: 408-222-8888 www .supertex.com 10 hv5122 doc.# dsfp-hv5122 a092908 44-lead plcc package outline (pj) .653x.653in body, .180in height (max), .050in pitch symbol a a1 a2 b b1 d d1 e e1 e dimension (inches) min .165 .090 .062 .013 .026 .685 .650 .685 .650 .050 bsc nom .172 .105 - - - .690 .653 .690 .653 max .180 .120 .083 .021 .036 ? .695 .656 .695 .656 jedec registration ms-018, variation ac, issue a, june, 1993. ? this dimension is a non-jedec dimension. drawings not to scale. supertex doc. #: dspd-44plccpj, version d092408. .150 ma x .048/.042 x 45 o 1 .075 ma x 6 40 d d1 e1 e to p v iew horizontal side v iew v iew b a a2 a1 seating plane e b note 1 (index area) .056/.042 x 45 o .020max (3 places) .020 min ve rtical side v iew v iew b note 2 44 b1 base plane notes: a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. actual shape of this feature may vary. 1. 2.
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